Circuit diagram for ULF and ELF Receiver

Frequency range DC to 30 hertz

This circuit was designed as an all purpose ULF and ELF receiver with a frequency range from DC to 30 hertz.  The signal from both leads of the antenna array are connected to J3. The polarity is not a concern.  The signal then travels to pins 2 and 3 on U5 which is a high impedance differential instrumentation amplifier. This chip's gain is controlled by a single variable resistor, R3. The formula if only a standard resister is used is:  Gain equals 1 + 50K divided by the gain resistor. 

The combined signals travel then from pin 6 to U3 which is a buffer amplifier, two pole low pass filter and signal amplifier. From pin 14 on U3, the partially filtered signal travels to U2 and U1 which are 5 pole Butterworth low pass filters in cascade.   The LTC1063 ICs are clock controlled and the frequency is set at 3000 hertz by R9. This configures the chips to have a cut off frequency of 30 hertz.  The clock ratio is 1/100.

The IC U4, consists of a X5 amplifier, buffer and another 2 pole analog low pass filter.  R17  is the final gain control for the desired output voltage.   U4B is a 2 pole low pass filter which removes any residual clocking pulses from the signal which may have been caused by U1 and U2. 

          The circuit below is a schematic of the power supply needed for the above receiver.    This will furnish plus and minus 5 volts DC. 

The schematic below shows the placement and wiring of the antenna arrays.

  Charlie Plyler 2000 - 2003